Search for: All records

The dimmest and most numerous outlier of the Type Ia supernova population, the Type Iax event, is increasingly being found in the results of observational campaigns. There is currently no single accepted model to describe these events. This 2D study explores the viability of modeling Type Iax events as a hybrid C/O/Ne white dwarf progenitor undergoing a deflagration using the multiphysics software FLASH. This hybrid was created using the stellar evolution code MESA, and its C-depleted core and mixed structure have demonstrated lower yields than traditional C/O progenitors in previous deflagration-to-detonation studies. To generate a sample, 30 “realizations” of this simulation were performed, the only difference being the shape of the initial match head used to start the deflagration. Consistent with earlier work, these realizations produce the familiar hot dense bound remnant surrounded by sparse ejecta. Our results indicate that the majority of the star remains unburned (∼70%) and bound (>90%). Our realizations produce total ejecta yields on the order of 10⁻²–10⁻¹M_☉, ejected⁵⁶Ni yields on the order of 10⁻⁴–10⁻²M_☉, and ejecta kinetic energies on the order of 10⁴⁸–10⁴⁹erg. Compared to yields inferred from recent observations of the dimmest Type Iax events—SN 2007qd, SN 2008ha, SN 2010ae, SN 2019gsc, SN 2019muj, SN 2020kyg, and SN 2021fcg—our simulation produces comparable⁵⁶Ni yields but too-small total yields and kinetic energies. Reignition of the remnant is also seen in some realizations.

 

Ookami [3] is a computer technology testbed supported by the United States National Science Foundation. It provides researchers with access to the A64FX processor developed by Fujitsu [17] in collaboration with RIKΞN [35, 37] for the Japanese path to exascale computing, as deployed in Fugaku [36], the fastest computer in the world [34]. By focusing on crucial architectural details, the ARM-based, multi-core, 512-bit SIMD-vector processor with ultrahigh-bandwidth memory promises to retain familiar and successful programming models while achieving very high performance for a wide range of applications. We review relevant technology and system details, and the main body of the paper focuses on initial experiences with the hardware and software ecosystem for micro-benchmarks, mini-apps, and full applications, and starts to answer questions about where such technologies fit into the NSF ecosystem.